Exemplary embodiments relate to a semiconductor memory device and a method of operating the same.
Semiconductor memory devices are storage devices in which data can be stored and from which the stored data can be read as needed. The semiconductor memory devices are chiefly divided into random access memory (RAM) and read only memory (ROM). Data stored in RAM is lost when power is not supplied. This type of memory is called volatile memory. Meanwhile, data stored in ROM is not lost even when power is not supplied. This type of memory is called nonvolatile memory.
The functions of semiconductor memory devices are gradually improved through the high degree of integration and an increase in the capacity and the chip size.
Recently, in order to further increase the degree of integration of semiconductor memory devices, active research is being done on a multi-bit cell which is able to store data in a single memory cell. This type of the memory cell is called a multi-level cell (MLC). A memory cell capable of storing one bit is called a single level cell (SLC).
FIG. 1 is a cross-sectional view of known memory cells.
Referring to FIG. 1, the memory cells MC1 to MC3s include floating gates FG and control gates CG formed over a substrate.
The substrate is divided into active regions and isolation regions. The active region is a region in which a channel is formed when operating voltages are supplied to the control gate CG.
Coupling is generated between the memory cells MC1 to MC3.
In FIG. 1, ‘A’ indicates coupling between the floating gates FG, and ‘B’ indicates coupling between the floating gate FG and the channel of the active region.
With a reduction in the size of a memory chip, a gap between the memory cells MC1 to MC3s is narrowed, thereby resulting in a reduction in the active region.
In a process of manufacturing memory cells, the concentration of impurities is decreased with a reduction of the active region and so a depletion region is reduced.
If the depletion region is reduced, current Ioff through a memory cell is increased even though it is turned off, and interference resulting from a bit line can become worse.
In other words, in case where the memory cells MC2 and MC3 are programmed with the memory cell MC1 being in a program state and the neighboring memory cells MC2 and MC3 being in an erase state, the threshold voltage of the memory cell MC1 may rise because of coupling influence due to a shift in the threshold voltages of the memory cells MC2 or MC3.